IC 74LS76 Dual J-K Positive-Edge-Triggered Flip-Flop
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IC 74LS76 Dual J-K Positive-Edge-Triggered Flip-Flop, Dual J-K Positive-Edge-Triggered Flip-Flop DIP-16Offers individual J, K, Clock Pulse, Direct Set, and Direct-Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.